Hi Tosei,
Thanks a lot for your response. Please see my comments below:
HdrChopper wrote on Jan 29th, 2009, 5:32pm:Hi Vivek,
- Much smaller offset and 1/f noise levels compared to their MOS counterparts (can be as smaller as 20x compared to MOS input stage)
At some point offset and noise could be important when it comes to consider the accuracy of you ADC. Having such high features might allow you to not chop (or autozero) your amplifiers if low offset / noise was a requirement, therefore simplifying your design.
Indeed, 1/f noise reduction would be achieved very nicely with BJTs, but mostly, this is not a very big issue in wideband pipelined ADCs as the thermal noise dominates much more, offset is usually also not a big problem. Of course, it is always nicer if you don't need to do autozeroing just for removing offset and 1/f.
Quote:- The input impedance could be highly increased by using base current cancellation techniques, which I'm not sure why you say that will add more noise. I actually used them more than once without degrading the overall noise performance of the amplifier (could you please clarify a little bit more?)
I meant that the extra branches added for base current compensation would increase the noise. Of course, the noise is probably not increased a lot, but I would expect that the base current compensation network needs to have a very high bandwidth if I use it in a pipelined ADC because this must also settle quickly. So, this runs off more current and injects more noise at the opamp input. Or am I mistaken?
Quote:In case you are thinking of using switched-cap stages then the base current (even with the cancellation circuit) might be a problem if you get some offset: if everything was perfectly balanced same base current would go to the input switched capacitors not generating any differencial droop. A more realistic case will be such that your base currents do not perfectly match and therefore might get some problems from there.
Yes! this is the issue. I know that for lower resolutions like 10 bits or so, people have managed to get away with the residual errors from the base current but I am not sure what can be done for higher resolution levels.
Quote:If your stage is CT (say you have resistors at the input) then things are easier since - even without any base current cancellation - you could balance pretty well the impendace seen by both input bases to minimize in this way the input referred offset.
Ah! but you cannot make a pipelined ADC with CT stages.
Quote:- Concerning 2. you could still use NPNs on the second stage with input NMOS devices going into a folded cascode load. In that way you solve the headroom problem.
You mean that the N-side active load and cascode devices are realized with NPN. This of course needs less headroom but is terribly noisy, because BJTs always have Gm=Ic/Vt, which is the exact opposite of what one wants in active loads. I think the real advantage would be if one could use BJTs where higher Gm is needed.
Quote:Please consider the high impedance node will have somehow
smaller impedance than if you used a MOS second stage, due to the smaller input impedance of your NPN. If you use Miller compensation that will mean your dominant pole will be of higher frequency, which is good from the GBW optimization perspective but is walking towards more dificult stability conditions.
True, but maybe there is some way to optimize things. I see 2 advantages of using NPN as the second stage Gm: (1) Higher Gm for lower current and 2nd pole is pushed out easily. (2) RHP zero is avoided or atleast made insignificant with a BJT, making compensation easier. The disadvantage as I already wrote is that one needs to use a PMOS for the input of the 1st stage, which is slower and noisier (due to usually larger Gm of its NMOS active load).
Nonetheless, thanks a lot. If I can figure out a good way to overcome the base current issue (that's what haunted all those who tried to use BJTs in switched-cap filters and forced them to move to MOS where that works naturally).
Maybe I should not try to make SC circuits with BJTs.
Regards,
Vivek