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jdac_18

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Verilog DAC current source model
Feb 02^nd, 2009, 5:24am

I am working on making a model in verilog for a cascoded current source (for a current steering dac) excluding the switch, which I will make later. The purpose of this is to speed up the simulation time, so I can work on calibration.
I am using a simple model of a ideal current source in parallel with a resistor and a capacitor. I put in verilog a simple equation:
iout <+ Iin - V(in, out)/R - C*ddt(V(in, out))
R = 9.91M
C = 100fF (Cgd+Cdb)

The problem is that the step size when turning on a switch is too small when comparing it to the mosfet implementation.
I am not sure if I have the C and R values right or the equation i am using is too simple. Is there a more complex equation needed?

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Andrew Beckett

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Re: Verilog DAC current source model
Reply #1 - Feb 3^rd, 2009, 8:59pm

Given that what you put in your post can't possibly be the model (it's not syntactically correct), it's hard to say. Perhaps it would be better to post the whole model?

BTW, this post is really in the wrong board - it should have been under http://www.designers-guide.org/Forum/YaBB.pl?board=verilogams. I'm sure Ken will move it at some point ;)

Regards,

Andrew.

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ywguo Community Fellow Offline Posts: 943 Shanghai, PRC	Re: Verilog DAC current source model Reply #2 - Feb 3^rd, 2009, 11:19pm Hi jdac_18, What do the symbols mean in the verilog-AMS model? I don't know what in/out stand for? Is R paralled with the ideal current source? Yawei
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jdac_18

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Re: Verilog DAC current source model
Reply #3 - Feb 3^rd, 2009, 11:56pm

real parameter R = 9.91e6;
real parameter C =1e-12;
branch (vdd, outi) resi;

analog begin

I(outi) <+ I(ini) -V(resi)/R - C*ddt(V(resi));

ini is input
outi is output
resi is defined be the branch above
this is a snipit of the code. R and C are in parallel with the an ideal current source. The problem is the settling time is too long as well as the step size is hard to determine.

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Andrew Beckett

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Re: Verilog DAC current source model
Reply #4 - Feb 4^th, 2009, 3:11am

Perhaps I've not got my brain in this morning, but your code is measuring the voltages across the branch resi which is between vdd and outi, but the current output is between outi and 0 (i.e. ground). That's not quite (I think) what you describe (i.e. R and C in parallel with the source).

Did you mean to have:

Code:

I(outi)<+I(ini)+V(outi)/R+C*ddt(V(outi));

(this may not be right either, but I'm not entirely sure what you're trying to do here).

Regards,

Andrew.

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ywguo

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Re: Verilog DAC current source model
Reply #5 - Feb 4^th, 2009, 6:48am

Hi jdac_18,

What I think of is the same as what Andrew said.

I don't know your exact set up for the simulation. How much is the current value for each of the current source? What is the required settling time? However, C = 1e-12 is a quite large value considering the DAC may have a lot of unity current source.

Yawei

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jdac_18

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Re: Verilog DAC current source model
Reply #6 - Feb 4^th, 2009, 6:53pm

Hello,
Thank you for all the help so far. I am making a 10bit dac 4 bit binary 6 bit thermometer in a 90nm process. One LSB current source is 20uA and one unity current source is about 320uA. Settling time should be within a 100ps. I checked the capacitance again, and this time i get around 10fF for a unity current source, so its considerably smaller.
I simulated what Andrew said and it seems to be working with respect to changing with the decoder output, just the step sizes and the starting point are different from the mos implementation. I am guessing this must be an impedance issue, your advice on this would be much appreciated.

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boe

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Re: Verilog DAC current source model
Reply #7 - Feb 5^th, 2009, 4:10am

Hi jdac_18,
For your application, you need a model that models both large-signal and small-signal behaviour.
You get an offset in the current if you do not take the voltage drop across the MOS into account (due to current through your resistor).
Also, your model
Code:

branch (vdd, outi) resi;

seems to indicate a pMOS source, which should be referenced to vdd (doesn't matter for small-signal analysis, but may shift your starting point)...

BOE

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jdac_18 Junior Member Offline Posts: 12	Re: Verilog DAC current source model Reply #8 - Feb 5^th, 2009, 5:52pm Thank you for your input. You are correct that I am using a pMOS source. I understand the small signal, taking into account the rds and the overlap capacitance, but how do you take into account the large signal as well?
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boe

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Re: Verilog DAC current source model
Reply #9 - Feb 6^th, 2009, 2:39am

The model Andrew suggested will provide the current into pin ini at the output pin outi for V(outi)=0 and increases output current with increasing output voltage (measured against ground!).
You need a model that fits your MOS implementation over the output voltage range of interest, so I suggest you simulate your real MOS current source and your model with a DC voltage source at the output and do a DC sweep over Voutmin to Voutmax.
I suggest you use a model of the type
Code:

I(outi,vdd)<+I(ini,vdd)+V(outi,vdd)/R+C*ddt(V(outi,vdd));

and add an offset current to compensate for the fact that a real MOS current source will not provide I(Ini) at VDS=0V.
The simulation will also enable you to estimate if you need to model the non-linearity of your current source (compare NL of current with DAC NL requirements)...

BOE

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jdac_18

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Re: Verilog DAC current source model
Reply #10 - Feb 8^th, 2009, 8:58pm

Thank you for the help.
I changed the model, and added the DC offset, now the starting points are the same. The only problem remaining is the step size. The mos implementation has around a 200uA increase, while the model is about 300uA. I attempted changing the capacitance in the model, but there is a negligible change.
Also, wouldn't doing a DC simulation, sweeping the output not take into account the output impedance from the capacitor?

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boe Community Fellow Offline Posts: 615	Re: Verilog DAC current source model Reply #11 - Feb 9^th, 2009, 7:47am Of cource DC simulations will not cover cap influence; but I like to have a good DC model before I start to work on AC/transient parameters... PS: Also, you should make sure the operating conditions (esp. input current) are the same.
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