Dear all,

For the layout of an analog circuit there are some well-known best practices.
But what happens when you don't follow these guidelines? Can you assess this
qualitatively and if so, how?

As an example, consider a current mirror where the device sizing is OK with regard
to random mismatch/systematic mismatch.

How much would the matching be derated if one would not place these transistors close together? Or make their orientation perpendicular? Etc.
Any way to put a number on that (derating factor)?

Kind Regards

Peter

Peter,

I think you should distinguish between local and distance mismatch. Unfortunatly, distance mismatch is typically not characterized in the DRM and there is also only very little literature available. However, you can try to find a publication which gives number for distance mismatch for a similar technology and compare it to the local mismatch data you have from your fab.

But when you have small (especially minimum length) devices, I think that the benefit of common centroid is only limited. Dummies on the other hand I think are important due to well-proximity effects, STI etc.

Cheers

Probably you CAN derate the matching by bad layout - but I expect that techniques like interdigitized-structures and common-centroid won't bring much improvement unless you have very large devices.

Cheers