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ideal clock not ideal in simulation (Read 2448 times)
seahs
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ideal clock not ideal in simulation
Mar 09th, 2009, 10:29am  


I used the vpulse in analog. the clock is used to drive many TGs in a sample and hold amplifier. How come it became not ideal in simulation?
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Andrew Beckett
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Re: ideal clock not ideal in simulation
Reply #1 - Mar 9th, 2009, 2:57pm  
Can you post the netlist. I doubt very much what your plotting is directly the output of the vsource.

Regards,

Andrew.
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Ken Kundert
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Re: ideal clock not ideal in simulation
Reply #2 - Mar 9th, 2009, 10:00pm  
TGs?
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seahs
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Re: ideal clock not ideal in simulation
Reply #3 - Mar 9th, 2009, 10:10pm  
Ken Kundert wrote on Mar 9th, 2009, 10:00pm:
TGs?


Transmission gates
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