Hi, All,

I'm currently working on a transistor layout. When I did the LVS for an individual transistor (the substrate is tied to the source terminal), it reported three errors on missing ports (gate, source and drain). I actually defined these ports by "connectivity->update->components and nets->layout generation->generate I/O pins", and the pin labels are also defined in the 'pin' layer.

When I put this transistor in a higher-level circuit block, it reported the transistor part is correct, although with a warning about "Extra ports in source: Gate". Now I'm confused. Anybody encountered similar problem?


Best Regards,
Ian