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The Designer's Guide Community Forum › Simulators › Circuit Simulators › Offset-Simulation of Comparators paper / implementation in eldo

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Offset-Simulation of Comparators paper / implementation in eldo (Read 3008 times)

AnalogDE Senior Member Offline Posts: 137	Offset-Simulation of Comparators paper / implementation in eldo Mar 16^th, 2009, 10:15am I have read the white paper on Offset-Simulation of Comparators on this site and I would like to implement it using eldo and a post-processing script. I'm wondering if anyone has already done this here and is willing to share their eldo input deck and/or post-processing script? Thanks in advance.
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weber8722 Community Member Offline Posts: 95	Re: Offset-Simulation of Comparators paper / implementation in eldo Reply #1 - Mar 17^th, 2009, 7:30am Is this for a latched comparator (i.e. with clock) or for a continous-time comparator. The TB are quite different. In Cadence ahdlLib there is a veriloga view helping to implement such TB. Bye Stephan
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AnalogDE Senior Member Offline Posts: 137	Re: Offset-Simulation of Comparators paper / implementation in eldo Reply #2 - Mar 17^th, 2009, 10:33am This is for a latched comparator.
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AnalogDE Senior Member Offline Posts: 137	Re: Offset-Simulation of Comparators paper / implementation in eldo Reply #3 - Mar 17^th, 2009, 2:34pm Nevermind, I was able to code up a simple perl script and eldo testbench. Thanks anyway.
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