Hi everyone,

This ADC is a 100kS/sec 14bit SAR ADC. If we give a constant voltage at the input of ADC, the ADC could achieve 14bit accuracy. (This voltage is given from E5052A and this voltage source is ideal enough for us). But if we insert a 10kOhm resistor between the voltage source and the ADC input, the ADC will degrade to only 8bit accuracy. This means a voltage noise with several millivolts presented a the ADC input. This may due to the weak driving ability of the ADC input node. But could anybody help explain how this huge level of voltage noise is generated?

Any answers are appreciated!
-Ryan

Hi Berti,

You are right. This has nothing to do with noise indeed. In fact we have got a very large DNL. And the settling is not enough. But the charges will never be released by using a special technique on S/H timing control. Even if the settling is not enough, we will eventually get a accurate code after several S/H periods. And this method has been verified by simulation. Of course, we don't know whether there are other side-effects missed. This is an irregular way to implement ADC.

Another irregular thing we've done is that the node for ADC input is a high impendance point. And the capacitor to hold the input voltage is 0.4nF while the sampling capacitor is only 0.5nF. These two capacitances are comparable. And the 10kOhm resistor mentioned in previous post is connected between these two capacitors.

I wonder if there are some other side-effects introduced by the two irregular method? And other information is still needed?

Thanks,
-Ryan