Hi all,

I am designing a pre-amp for neural recording applications in CMOS 0.18u process.

The input signal has a magnitude in the range 1uV to 1mV and has a bandwidth of 1KHz.

The pre-amp has to amplify the signal by a factor of 100 before it could be converted to digital.

Due to the electrode offsets the input can have sufficient DC offsets to saturate the op amp hence we are using AC coupling at the input.

To reduce the low frequency noise I wish to use the chopping technique but I run into problems due to the AC coupling.

The op-amp has a bandpass characteristics with rollovers at 1Hz and 500 KHz respectively.

Due to the high time constant of the high pass pole the chopped (up-converted) signal takes a lot of time to settle down and hence the output is very distorted.

If I assume the input has not offset and set it to 0 the chopping techniques works fine.

Is there a way to fix this problem?
How do we chop an AC-coupled op-amp?

Any help in this regard would be highly appreciated.

Regards,
Bhupendra

Hi Reiner,

Thanks for the response.


I think the best way is to use a chopped opamp and connect a non-inverting amp, gain defined by resistor feedback.

I initially decided on resistor feedback only but we need to cancel out the DC offsets or else we run into op-amp saturation.

I am pasting the circuit here. The two small blocks are the choppers.

The problem is that if I chop right at the input then I am modulating the signal as well as the input offset both to the chopping frequencies and hence the high pass is no able to block the DC.

This modulated DC offset (of the electrodes) is them amplified and appears at the output (and if its large enough can saturate the op amp).

I was wondering if there is anyway I can first high pass the signal and then modulate it?

Hope the picture of the circuit helps.

Regards,
Bhupendra

Hi Bhupendra,

I just replied to your message the following....

From what you described it looks to me you are chopping the amplifier outside the feedback loop. Is this correct? If that is the case then your chopper performance will be severely limited by the already limited bandwidth of your loop. This translates into gain inaccuracies after the post chopper filtering.
In any chopper-stabilized amplifier the first requirement it has to be fulfilled is the BW of the system you are chopping has to be at least 5X larger than the chopper frequency. This is not fulfilled in your case if I interpret it correctly (may be a drawing of your circuit would help).

A nice way to overcome bandwidth limitations on chopped opamps is to avoid the demodulation right on the opamp outputs and do it inside the loop. For example, let´s assume you have a two-stage opamp. The main offset and 1/f contribution will come from the preamp or first stage.
So you are going to chop just this stage: the modulation switches should be connected right to the inputs of the opamp (virtual ground), while the deomdulation switches should go right before the input of your second gain stage. If you use for example a folded cascode first stage you could demodulate the currents going into the cascode devices prior to go to the second gain stage (which could for example be a Miller stage for stabilizing the opamp).
Be aware of the fact that the second gain stage is not chopped and therefore it will contribute to the offset of the opamp (non-chop-able offset). However if your first stage has enough gain, the non-chopped second stage offset contribution will be negligible when referred to the input. A rule of thumb for fulfilling this requirement is that the first stage gain has to be larger than the closed loop gain.....

You can take a look at these papers where this technique is used:

M. Sanduleanu, et.al. “Low Power, low voltage chopped amplifier with a new class AB output stage for mixed signal applications”. Proc. of the ProRISC Workshop on Circuits, Systems and Signal Processing 1997.

P.K. Chan, et.al. “A CMOS chopper-stabilized differential difference amplifier for biomedical integrated circuits”. The 47th IEEE International Midwest Symposium on Circuits and Systems

If I can remember more related references I´ll let you know.
Hope this helps

Tosei

Hi Tosei/Reiner,

Thanks a lot for your inputs.

I tried implementing the chopper inside the loop (as suggested) and demodulated the signal at the low impedance nodes (in the folded branch).

There were a couple of observations:

i) as we can see there is a feedback resistor that connects the output and the input. The resistor serves two purpose here:

- it sets the input common equal to the output common mode
- it forms a high pass pole (~10Hz) with the feedback cap that filters out any low frequency artifacts and the DC offsets from the input.

As is evident this is a very high resistance (~100G) and has been realized by using the PMOS device as pseudo-MOS-bipolar resistor.

In absence of the chopper the feedback factor for DC is 1 (unity feedback)

Now when we add a chopper at the input of the op-amp (at the gates of the input diff pair) the off-transistors of the chopper form a feedback network with this high resistance as the off resistance is of the same order as the feedback resistance.

Normally if a low resistor was in the feedback path the feedback factor has still been ~ 1 but in this case it becomes < 1 and thus reduces the loop gain which kills the performance of the op-amp.

I cannot reduce this feedback resistance as the application requires me to have the filter characteristic with a high pass cutoff at ~ 10Hz.

I tried to increase the off resistance by increasing the length of the switches but still could not get the beta close to 1.

Any suggestions/comments on this?


ii) The other problem is again due to this high resistance. When I do an AC simulation and plot the gain from the gate of the input diff pair to the folded branch I see two poles (one at ~ 5 KHz and the other at ~ 50KHz).

The corner frequency for noise is around 2 Khz and the signal bandwidth is 1 KHz so I need to pick the chopping frequency > 2 KHz. I picked 50 Khz so the low pass filter specs could be relaxed and I get good attenuation.

The problem with picking this frequency is that it is > the 1st pole.
This means lower gain and 90 phase shift which kills the chopping performance.

I can burn more current to push this pole out but is there any way I can do this w/o burning more power?

Let me know if a schematic is required and I can post the same here.

Regards,
Bhupendra

Hi subgold,

The chopper is still inside the loop and the feedback is connected to the chopper input and not the the gates of the input diff pair.

By using techniques like sub-threshold biasing and using a diode connected MOS with VGS=0 (MOS-bipolar pseudo resistor) one can get resistances of the order of 10^12.

Even with high resistance the circuit is not open and serves the two purposes I mentioned in my previous post.

Regards,
Bhupendra

Hi Tosei/Others,

I appreciate your concerns wrt to the use of 10^12ohm resistor in the feedback.

I would assume the parasitic input resistance of the MOS gates is high enough to ensure the feedback impedance is smaller otherwise I would see a beta < 1 in my AC simulation (which is not the case). Do you think these effects have not been modeled and might show up in silicon?

Also linearity is not much of an issue for me as the closed loop gain is set by the ratio of the cap and not this resistance.

The only thing that this resistance sets is the high pass pole of the filter (1/2*pi*Rfb*Cfb) and with signal swing at the o/p the resistor value will change and might move this pole. This is okay as long as the pass band still covers the signal bandwidth. Besides this could be adjusted by trimming the input and feedback caps.

In other implementations of the neural amplifier people have used subthreshold biased MOS or MOS in triode region to implement a high resistance. These resistances are usually of the order of few hundreds of megaohms and are prone to signal swing dependent distortions.

A pseudo-MOS-bipolar offers the highest resistance with minimum area and hence was picked for this design.

The gain of the system is ~100 and the max input signal amplitude is ~ 1mV which means the max o/p swing is ~ +/-100mV and most MOS-bipolar resistors can tolerate such swing w/o appreciable decrease in the resistance value.

One of the important spec for this application is to realize a high-pass characteristic with roll over at ~ 1Hz. This is hard to realize and a pseudo-mos-bipolar resistor is one of the possible ways of realizing such a low frequency pole w/o blowing up the area.

A switched cap implementation sounds attractive but I have a few concerns with the same:

a) power - might go up if SW is employed
b) may be more noisy (switching noise, feedthrough, injection)
c) area

The idea is to have an ultra low power low noise preamp as it would be used in large numbers (~ 64 channels).

Is there any paper/text you can point me to that talks about switched cap bandpass filters (closer to my specs) that employ chopping technique so I can have a look at their noise, area and power numbers and make a judicious decision.

I hope this background on the application and rationale behind the choice of pseudo-resistor might help everybody in appreciating the problem better.

Regards,
Bhupendra

Have you read a paper from Enz & Temmes ??
I guess you should read that. It has a lot of information about chopper stabilization, especially about the implementation part.

The distortion, you were taking about in the out could be due to non-linearity introduced by the switches in the chopper amplifier or the delay introduced by the Amplifier can cause such distortion as modulation and demodulation aren't synchronized due to delay introduced by the amplifier.