Bhupendra wrote on Mar 30th, 2009, 10:19pm:Hi Tosei/Reiner,
As is evident this is a very high resistance (~100G) and has been realized by using the PMOS device as pseudo-MOS-bipolar resistor.
In absence of the chopper the feedback factor for DC is 1 (unity feedback)
Now when we add a chopper at the input of the op-amp (at the gates of the input diff pair) the off-transistors of the chopper form a feedback network with this high resistance as the off resistance is of the same order as the feedback resistance.
Normally if a low resistor was in the feedback path the feedback factor has still been ~ 1 but in this case it becomes < 1 and thus reduces the loop gain which kills the performance of the op-amp.
I cannot reduce this feedback resistance as the application requires me to have the filter characteristic with a high pass cutoff at ~ 10Hz.
I tried to increase the off resistance by increasing the length of the switches but still could not get the beta close to 1.
Any suggestions/comments on this?
Even if you do not consider the chopper switches I would not use 10^12 resistors made out of MOS devices becuase of two reasons:
1) Actual opamp will have an input impedance similar or even lower than 1Gohm when looking at the input gates due to parasitc resistances. Therefore you will never get your 1X DC gain factor. In other words, the feedback network has suc high output impedance that the opamp will not be even close to an ideal behavior (the feedback network must have much lower impendance than the one of the opamp input)
2) the MOS resistance might not be linear. So depending on your linearity requirements (which I think might be important since you are using feedback) and your signal swing you might get some distortion.
The best way to go her is by using switched cap techniques. It perfectly suites your requirements for very low cut of frequency and is totally compatible with chopping technique
Bhupendra wrote on Mar 30th, 2009, 10:19pm:ii) The other problem is again due to this high resistance. When I do an AC simulation and plot the gain from the gate of the input diff pair to the folded branch I see two poles (one at ~ 5 KHz and the other at ~ 50KHz).
The corner frequency for noise is around 2 Khz and the signal bandwidth is 1 KHz so I need to pick the chopping frequency > 2 KHz. I picked 50 Khz so the low pass filter specs could be relaxed and I get good attenuation.
The problem with picking this frequency is that it is > the 1st pole.
This means lower gain and 90 phase shift which kills the chopping performance.
Where is the 1st pole generated? do not look at the voltage transfer function inside the loop: since demodulation is done on the folded currents you should care about the current bandwith up to the demodulation switches. My gut feeling is that you are generating the first pole once you converted such currents into voltage.
NEvertheless, since you are chopping inside the loop, assuming you have a large open loop gain, such distortion due to finite banwidth will not be observed at the output due to the feedback nice property of improving such type of errors. I would not care to much about such distortion due to finite BW if you open loop gain is large.
Regards
Tosei