Hi all,

I am designing a VCO using a 0.18-um CMOS. In my design-kit I don't have any ESD protected pads. What I have is only RF pad, which is just a stack of metal layers. So, for example, for the input terminal of my current mirror used to bias the circuit. Since this input consists of the gate terminals (shown in the figure) which are brought out directly to the pad, and to the outside world, I put a resistor (1k in this case) between the pad and the two gate terminals. I hope that this at least offers a protection against ESD. It should be better than routing this terminal directly to the pad.

The problem is, since I need to use a big enough resistor (1k) to make this protection, the bias current will be too low for the VCO if I bias the current mirror (by external voltage source) with Vdd = 1.8 V.

To obtain an enough bias, I need to increase this bias voltage to about 6 V. What I am wondering is that, since this voltage is higher than the breakdown voltage of this technology, will this affect the circuit ?

Actually, by using the Vbias = 6 V, the voltage at the input of the current mirror remains at about 1 V, which is below the breakdown voltage.

Could someone recommend me that what I am doing is right or wrong
Cheesy

I think that the, when regarding to the breakdown voltage, we should regard to the voltage that actually appears to the transistors. Since 6 V is not at the transistors, should this be OK ?

Thanks a lot guys Cheesy

DYL

Thanks a lot for your confirmation, TheChopper