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neoflash Community Fellow Offline Mixed-Signal Designer Posts: 397	Reduction and Apr 02^nd, 2009, 9:03am what is the definition of "reduction and" (&) in verilog ams? thanks.
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Geoffrey_Coram Senior Fellow Offline Posts: 1999 Massachusetts, USA	Re: Reduction and Reply #1 - Apr 3^rd, 2009, 3:59am It's a bitwise operator. See section 4.2.9 of the Verilog-AMS LRM, version 2.3 Did you have a specific question about how it handles signed vs unsigned or unequal bit length arguments?
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neoflash Community Fellow Offline Mixed-Signal Designer Posts: 397	Re: Reduction and Reply #2 - Apr 3^rd, 2009, 6:07am Thanks. Just a little confused with what "reduction" refers to?
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Ken Kundert

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Re: Reduction and
Reply #3 - Apr 3^rd, 2009, 9:42pm

Reduction & is applied to one argument and returns the logical and of all the bits in that argument. So it always returns a single boolean value.

This contrasts to the bitwise & that applies to two bit vectors, and return a bit vector where each bit is the logical and of the corresponding bits in the arguments.

So if A is 2'b11 and B is 2'b01, then &A is 1, &B is 0, and A&B is 2'b10. The first two are reduction &, the last is bitwise &.

-Ken

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Geoffrey_Coram Senior Fellow Offline Posts: 1999 Massachusetts, USA	Re: Reduction and Reply #4 - Apr 6^th, 2009, 5:33am Oops, sorry, I was completely wrong. I should have pointed you to 4.2.10 Reduction operators The reduction operators can not be used inside the analog block and only have meaning when used in the digital context. Information on these operators can also be found in the IEEE std 1364-2005 Verilog HDL. -- or you can just read Ken's post.
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