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VDD/VSS ESD protection issue (Read 1550 times)
trashbox
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VDD/VSS ESD protection issue
Apr 15th, 2009, 4:38am  
Hi all,
As the attachment, the left-side is a general vdd/vss ESD protection circuit. How the M1/M2 works when it is under Positive-mode ESD test as described in the right-side? Thanks in advance!

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loose-electron
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Re: VDD/VSS ESD protection issue
Reply #1 - Apr 17th, 2009, 10:41pm  
Those types of circuits require a large signal failure mechanism called "punch through" giving conduction from drain to source even though the gate threshold has not been exceeded.
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