Hello,

I've searched a bit around on the forum, but I can't find the answer I'm looking for so I hope it's OK that I start a new topic.

As the topic name states, I'm searching for good interstage matching techniques.

At the moment I'm working on a two-stage MMIC pHEMT LNA for a school project. I got a working circuit which fulfills all the requirements (so I'm not asking anyone to do my homework ), but I think I can improve my circuit by doing some proper interstage matching.

I've tried some different approaches, but I'm not sure if I'm doing things 100% correct, so I thought maybe someone in here could give me some hints.

This is one of the approaches I've tried so far:

1. Find Bias-point for both stages
2. Match input of stage one to Z_Opt
3. Run SP simulations for stage one ONLY at f_c (with no match on the output), and write down S22 at f_c
4. Match output of stage two to Z_L
5. Run SP simulations for stage two ONLY at f_c (with no match on the input), and write down S11 at f_c
6. Match S22 (output of stage one) to S11 (input of stage two) with lumped components
7. Remove input matching network on stage one and output matching network on stage two, and then math to the new Z_Opt on the input of stage one, and conjugate load on output of stage two.

I'm not sure if this is correct at all or not, but for me it seems like one possible approach, although the results I get doesn't confirm that  ::)

The other approaches basically builds on trying and failing in ADS, by just trying different matching networks for the interstage.

Any hints will be deeply appreciated

Best regards,

drgz

thanks a lot for your help! i will try it out this weekend and see if i can improve my results