aaron_do wrote on Apr 24th, 2009, 10:21pm:I was thinking that we can leave the output open circuit (or whatever the desired load is), and use a port at the RF input.
Is this setup ok for measuring Z11?
No, you are misunderstanding.
Resistance of "analogLib/port" surely acts as load in PSS of Cadence Spectre.
When you evaluate Z-parameters using PSP, you can't ignore this unpreferable load effects.
http://www.designers-guide.org/Forum/YaBB.pl?num=1231854969/5#5This is because PSP is slave analysis of master analysis PSS.
You yourself also mentioned this effects in PSS in your another comments.
If you create switch using Verilog-A which operations are OFF for PSS and ON for PSP, you can use PSP without loading at nodes.
Quote:// This module is valid only for Cadence Spectre
`include "discipline.h"
`include "constants.h"
module ac_switch(vp, vn);
inout vp, vn;
electrical vp, vn;
analog begin
if( analysis("ac", "pac", "qpac",
"xf", "pxf", "qpxf",
"sp", "psp", "qpsp",
"noise", "pnoise", "qpnoise") )
V(vp, vn) <+ 0.0;
else
I(vp, vn) <+ 0.0 ; // V(vp, vn) <+ 1.0T * I(vp, vn);
end // analog
endmodule
On the other hand, you can use ports directly to evaluate Z and Y parameters in conventional SP-Analysis as far as ports don't affect DC bias.
aaron_do wrote on Apr 24th, 2009, 10:21pm:Also, I was thinking that the LO leakage to either RF or IF ports can affect the operation and hence the Zin of the mixer.
Right.
http://www.designers-guide.org/Forum/YaBB.pl?num=1193135745/3#3aaron_do wrote on Apr 24th, 2009, 10:21pm:If you use a voltage source at the RF input the LO-RF leakage will be zero, so can this be an accurate measure of input impedance?
Impedance Probes don't shorten any terminals. See Fig. A.2 at page.32 of
http://www.rdmiddlebrook.com/downloads/GFTManual.pdfImpedance Probes are inserted like following.
[
Source_Impedance or Previous_Stages]=[
Diff_Imp_Probe]=[
Mixer]=[
Diff_Imp_Probe]=[
Next_Stages]
||
[
Diff_Imp_Probe]
||
[
VCO]
Here [
Diff_Imp_Probe] don't shorten [
Source_Impedance or Previous _Stages].
In this way, I can evaluate Zleft_diff, Zleft_comm, Zright_diff and Zright_comm at same time without any affect to original electrical connections of circuits.