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jtr6907

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a question about a Ultra Low-Voltage Ultra Low-Power CMOS Voltage Reference
May 05^th, 2009, 12:53am

Hi guys
I met some problems in the simulation process by spectre,schematic as follow(from a paper):

My problem is that the LNR is so bad!The output voltage changed about 10mv when supply voltage changed from 0.8v to 2V at room temperature which is changed only 6mv from 0.9v to 4V in the paper(experimental results).now I show you my detail transistor parameter as follows,
M1:id=26.7nA W/L=10um/10um vth=497mv
M2:id=100nA W/L=1.145um/10um vth=336mv
M3:id=26.7nA W/L=2.85um/10um vth=487mv
M4:id=100nA W/L=220nm/10um vth=245mv
M5:id=26.7nA W/L=1um/10um vth=-318mv
M6:id=26.7nA W/L=1um/10um vth=-318mv
M7:id=100nA W/L=17um/10um vth=-345mv
M8:id=100nA W/L=17um/10um vth=-345mv
M9:id=100nA W/L=17um/10um vth=-345mv
M10:id=100nA W/L=4um/10um vth=321mv
Vgs1,2=400mV Vgs3,4=450mV Vgs5,6=-400mV Vgs7,8,9=-350mV Vgs10=438mV(Vthn=340mv Vthp=-320mv)
,every transitor operates in the Saturation region(M1 M3 is operates in the subthreshold region).Would you please help me to check if there are any improper parameters?
� �Moreover,the transient response of my circuit is too slowly that the VREF need 1.5ms to settling.I can not understand this phenonmenon.Is my current is too small?
� �Thanks

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sheldon

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Re: a question about a Ultra Low-Voltage Ultra Low-Power CMOS Voltage Reference
Reply #1 - May 5^th, 2009, 5:27am

JTR,

� There is not a schematic attached to your append. Why do you
think that these devices are in saturation? The bias currents are
low, maximum of 100nA. How are you defining subthreshold operation?

� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �Best Regards,

� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � Sheldon

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jtr6907

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Re: a question about a Ultra Low-Voltage Ultra Low-Power CMOS Voltage Reference
Reply #2 - May 6^th, 2009, 3:58am

sheldon wrote on May 5^th, 2009, 5:27am:

JTR,

� There is not a schematic attached to your append. Why do you
think that these devices are in saturation? The bias currents are
low, maximum of 100nA. How are you defining subthreshold operation?

� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �Best Regards,

� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � Sheldon

Hi Sheldon!
sorry!The schematic had re-uploaded to the attach.Except M1,M3,every transistor is in saturation which vdsat is about 60mv,and these W/L is small(all parameter have been show above and M1,M3 are in subthreshold),so the small current can be achieved.My simulator is spectre so I can see the "region" from transistor parameter which display beside the transistor to define subthreshold operation.
Best Regards,

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29442282563941734011.jpg

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HdrChopper

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Re: a question about a Ultra Low-Voltage Ultra Low-Power CMOS Voltage Reference
Reply #3 - May 7^th, 2009, 7:04pm

jtr6907 wrote on May 5^th, 2009, 12:53am:

� �Moreover,the transient response of my circuit is too slowly that the VREF need 1.5ms to settling.I can not understand this phenonmenon.Is my current is too small?

Have you check the sizes of your start up circuit devices? It sounds like your start-up is not working as intended. Did you also tried different ramps on the supply voltage to check for any variability on such power-up time? If your start up current is too small you will need some time to charge all the parasitic capacitances..

Hope this helps
Tosei

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Keep it simple

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