Hi all,


this was my first try on creating a verilog-a model. I wanted to create a switch which is on for dc operating point type analyses such as dc, pss and the dc operating points of ac, sp, noise etc.

The code I used is based on the code given by pancho_hideboo in a previous post. Anyway this is the code i used.

Quote:


Unfortunately, the simulator doesn't seem to recognize the analysis type "static" as the switch is not closed when I use dc analysis. I wanted to double check so after a bit of experimenting i found that I could simply type in the CIW,

simulator('spectre)
analysis("static")

and it came up with the following message

Quote:


So on inspection we can see that the analysis type "static" is not on the list. However, when i typed in analysis("ac") it gave me the exact same warming even though analysis type "ac" is on the list.

I'm totally lost here. Does anybody know how I can fix this. I need to either create the switch in another way, or fix the setup issue which seems to exist.


thanks,
Aaron

Hi,


thanks for the reply. Sorry i really don't pay too much attention to the inner workings of the software so i'm not too sure about all the answers.

So believe i'm using cadence version IC5141USR5. Is that the version you're asking about? So i assume the dc voltage was able to propagate through the switch right? It isn't working for me. Furthermore if I change line 9 to

if( analysis("dc", "static"))

it still doesn't work. Isn't the "," sign supposed to act as an OR function? Note that if I do

if(analysis("dc"))

then the switch works. However, that will not work for the operating point calculated in the ac analysis.


thanks,
Aaron


P.S.  Is it possible that some component of the software hasn't been properly installed? If so where would I start looking? thanks!

Hi Geoffrey,


it is unable to work for a simple netlist. I used the same netlist as you did: a voltage source the analysis_switch and a resistor. The current does not flow through the switch for either ac or dc analysis. Seems to be unable to recognize the analysis type "static". My version of spectre is 6.1.1.133.

When I use
if (analysis("dc") || analysis("static") )
the analysis("dc") part works, but not the analysis("static").


thanks for the help,
Aaron

Hi Paul,


is there any way to confirm whether they are supported in my simulator? By the way what is the 2.3 LRM?

thanks,
Aaron

Could it be a setup problem with the verilog simulator?

aaron_do wrote on May 7^th, 2009, 5:28am:


Hi

It depends on the simulator I guess. Mentor Graphic's [my employer] ADVance MS will print a warning at compile time if the string is not one of the recognized ones.

Paul

I'm wondering where you're testing this. In the very first post you talked about typing:

analysis("static")

in the CIW. Well, that's not Verilog-A that's SKILL (or OCEAN). So the analysis function there is for setting up an analysis in an OCEAN script. There's no such analysis as "static" so it's hardly surprising that doesn't work.

I dont' know why analysis("static") wouldn't work in a VerilogA model in spectre; this has been supported for as long as I can remember.

Andrew

The best thing for OCEAN is to attend a Cadence OCEAN training class (OK, I'm biased, because I wrote the class).

But otherwise you could look at the OCEAN Reference in the installation:

 <ICinstDir>/doc/oceanref/oceanref.pdf

And also the SKILL Language User Guide:

 <ICinstDir>/doc/sklanguser/sklanguser.pdf

Or use cdsdoc (or cdnshelp if using IC61) to read these documents.

Regards,

Andrew.