Hello,

I am modelling the behaviour of a DCO after Staszewski in Verilog-AMS.

As there are no integer type ports in Verilog, i have a bus of logic ports that i use to read the digital control word from.

I would like this port to behave like a signed integer input, but it only interprets the input as unsigned. How can I make the input behave like it is a signed integer port?

An example code of the DCO is attached.

use the keyword "signed" on the wire where you declare it

from 1364-2005 paragraph 12.3.3:

Code:

input_declaration ::=
input [ net_type ] [ signed ] [ range ] list_of_port_identifiers 

if you used the signed keyword, the resulting integer will be treated just like a signed register.

Code:

`timescale 1ns / 1ps
`include "disciplines.vams"

module dco_1 (out, ps, ns, DCO_CONTROL);
    parameter real f0 = 100k from (0:inf);		// center frequency (Hz)
    parameter real kvco = 10k;			// gain (Hz/V)
    parameter real DCO_QUANT = 100p;		// period deviation per digital step
    input signed [7:0] DCO_CONTROL;			// digital control word
    input ps, ns;
    output out;
    electrical ps, ns;
    logic [7:0] DCO_CONTROL;
    reg out;
    logic out;
    real vin;
    real din;
    
    initial out = 0;

    always begin
	vin = V(ps, ns);
	din = DCO_CONTROL * DCO_QUANT;
	#((0.5e9 / (f0 + kvco * vin)) - ( din / 2))
	out = ~out;
    end
endmodule