Hi,

how to define a current source that does not drive an output node voltage above vdd?
i.e. I have a definition like: isource #(.dc(10u)) i0 (vdd,n1);

n1 is connected to the rest of circuit (basically set of switches and resistors). Now it so happens, that at certain conditions (switch turned on), current is drawn from the source and voltage at n1 begins to rise. However, once it rises to vdd, ideally no more current should be supplied.. but I observe that the node voltage continues to climb (current is continuosly supplied) What is way to prevent this? Is there something I can change in the manner in which the current source is defined?

thanks
K

Take a look at the "Current limited voltage regulator" on the Verilog-AMS page.

-Ken