hi somisetty,
                 i didn't understand your question because if you don't have any start up circuit and you want to check weather your ckt is working or not then initializes one of the node to some intermediate potential..

But you already have start up circuit,so during starting v- will be at zero potential so some current will flow through Q2 hence ckt  will start so don't think this need any internalization.

Thanks,
Rajasekhar.
 

Thanks for the reply...

i just like to elaborate my problem....

As you know the BGR has two stable operating points: One in which no current is flowing through the circuit which is the unwanted condition and the second is the desired operation .

To avoid the unwanted operating point we use a startup circuit.

I wanted to simulate the BGR without startup circuit by setting initial conditions to the nodes and see the unwanted condition…(so I did the below sim’s in DC and Tran)

1) I set the initial conditions of the nodes  Vc1 to VDD and V-/V+ to zero, performed the DC simulation and saw all the transistors went  into cut off (i.e which is the undesirable condition)

2) I set the initial conditions of the nodes  Vc1 to VDD and V-/V+ and  VDD ramping (ramp is 15u),performed the tran sim and, I see the BGR is not failing but building up the voltage to 1.2V.

My doubt is why the BGR didn’t fail in the tran sim.am I doing the tran sim correctly?

What I wanted to do next once I see the BGR failing in tran sim, I will connect the startup circuit and I should see the BGR building up the voltage (i.e., the startup is functioning)

Thanks again...

Thanks for the reply..

its my mistake..

2) I set the initial conditions of the nodes  Vc1 to VDD , V-/V+ to zero and  VDD ramping (ramp is 15u),performed the tran sim and, I see the BGR is not failing but building up the voltage to 1.2V.

okie...Thanku

i will try removing them and check it...

hi,
   how this startup ckt will effect psrr.Actually the basic property of the startup ckt is it should n't affect its normal operation, moreover settling time of bandgap independent of startup because once a startup ckt introduce disturbance, thats it BGR will take care remaining things(because while starting BGR is +ve feedback ckt so very fast).Why dont you use very simple startup which you can in razaavi?

Thanks,
Rajsekhar.

hi,
   how did you noticed that your startup is effecting settling time?
  and use the attached startup,it wont give any problem.

Thanks,
Rajasekhar.

no it wont waste power because top pmos has  very small aspect ratio (typically 1/20),or if you have any power budget allocate small fraction of power to startup ckt and you can play with that pmos aspect ratio.

Thanks,
Rajasekhar.