The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Jul 18th, 2024, 1:17pm
Pages: 1
Send Topic Print
voltage buffer design (Read 293 times)
subgold
Community Member
***
Offline



Posts: 97

voltage buffer design
May 26th, 2009, 2:19am
 
Does anybody have some ideas on how to design a voltage buffer which can cover VSS? the input range is from VSS to VDD/2.

of course, some sort of level shifter based structures can do the job. but are there any structures which have no level shifting? Due to the application, i want the buffer only to change the impedance, but not the voltage level.

thanks.
Back to top
 
 
View Profile   IP Logged
raja.cedt
Senior Fellow
******
Offline



Posts: 1516
Germany
Re: voltage buffer design
Reply #1 - May 26th, 2009, 2:28am
 
hi ,
   what do you mean by 'i want the buffer only to change the impedance, but not the voltage level'. I understood that you need a buffer which has to work from vss to vdd/2.For this one i think pmos based op amp will work.

Thanks,
Rajasekhar.
Back to top
 
 
View Profile WWW raja.sekhar86   IP Logged
subgold
Community Member
***
Offline



Posts: 97

Re: voltage buffer design
Reply #2 - May 26th, 2009, 2:59am
 
raja.cedt wrote on May 26th, 2009, 2:28am:
hi ,
   what do you mean by 'i want the buffer only to change the impedance, but not the voltage level'. I understood that you need a buffer which has to work from vss to vdd/2.For this one i think pmos based op amp will work.

Thanks,
Rajasekhar.


sorry i didn't formulate the question very clearly. the following stage of the buffer has a quite low input impedance, so i use the buffer only as a driver, but i want the dc level of the buffer input and output to be the same.

how will the pmos opamp work? i assume you mean a noninverting configuration of the opamp. that means both inputs and output of the opamp have to go down to VSS. but the output level cannot be lower than one Vdsat above VSS.

Back to top
 
 
View Profile   IP Logged
solidstate
Junior Member
**
Offline



Posts: 16
Munich, Germany
Re: voltage buffer design
Reply #3 - May 27th, 2009, 5:56am
 
The only way to drive really down to VSS while still having gain in your buffer is to operate the buffer from a supply lower than VSS... (think charge pumps).

What is driving the buffer in the first place? Is your signal source going all the way down to VSS? Maybe you can apply a DC shift there, to ease the buffer design...
Back to top
 
 
View Profile   IP Logged
subgold
Community Member
***
Offline



Posts: 97

Re: voltage buffer design
Reply #4 - May 27th, 2009, 10:06am
 
solidstate wrote on May 27th, 2009, 5:56am:
The only way to drive really down to VSS while still having gain in your buffer is to operate the buffer from a supply lower than VSS... (think charge pumps).

What is driving the buffer in the first place? Is your signal source going all the way down to VSS? Maybe you can apply a DC shift there, to ease the buffer design...


the signal source is really going down to vss, and a dc shift is also sort of buffer.

i think i asked a stupid question in the very first place. 'such circuit is impossible' is also a good answer to know Smiley
Back to top
 
 
View Profile   IP Logged
solidstate
Junior Member
**
Offline



Posts: 16
Munich, Germany
Re: voltage buffer design
Reply #5 - May 27th, 2009, 10:23am
 
Well, the circuit you had in mind is probably 'impossible', but solving your problem certainly is not. Maybe some more info about the signal source and the application could help us help you?
Back to top
 
 
View Profile   IP Logged
Berti
Community Fellow
*****
Offline



Posts: 356

Re: voltage buffer design
Reply #6 - May 27th, 2009, 11:50pm
 
Just an idea:
By having a resistive load you could operate the buffer lower than vdsat.

Cheers
Back to top
 
 
View Profile   IP Logged
raja.cedt
Senior Fellow
******
Offline



Posts: 1516
Germany
Re: voltage buffer design
Reply #7 - May 28th, 2009, 12:19am
 
hi Berti,
           could you please explain how resistive load decrease vdsat.
Thanks,
Rajasekhar.
Back to top
 
 
View Profile WWW raja.sekhar86   IP Logged
Berti
Community Fellow
*****
Offline



Posts: 356

Re: voltage buffer design
Reply #8 - May 28th, 2009, 2:07am
 
Consider just a simple differential pair with PMOS input transistors and resistors on the load side (or even only a source-follower) in unity-gain feedback configuration. This circuit should still work at relatively low input voltages.

Regards
Back to top
 
 
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.