Hi all,

From what I see in different PLL designs, typical N-divider output clock (as well as reference clock in case it's divided in R counter from quarz) has a duty cycle of approx. 20-25%. What's the idea behind it?

The only thing that comes to my mind is that the spectrum differences when compared to 50% duty cycle, maybe this helps against unwanted mixing, i.e. via substrate leakage etc. But when I look at FFTs of clocks with 20% and 50% dyty cycles, that does not look so straightforward to me..

Usually 50% duty cycle is attained by wide synchronous counters.  Faster counters can be obtained by ripple counters.  Since the PFD (In charge pump plls) usually work on the edges, the duty cycle is not as important.

Sorry to revive such an old topic but I am wondering about this myself. I am working with verilog-a models logic blocks (from cadence IC bmsLib) before going to circuit level design, and I noticed that the output of an integer-n divider is very short pulses but they have the correct frequency. What are typical methods to obtain 50% duty cycle from the divider? I was thinking to design the divider to output 2f_ref then feed that into a Master-Slave divide by 2 to get f_ref with 50% duty cycle. Are there other/better ways?