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Maximum on-chip variation in temperature for SOC (Read 2867 times)
cmos.analogvala
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Maximum on-chip variation in temperature for SOC
Jun 11th, 2009, 11:19pm
 
What is the maximum variation in temperature of two IPs on a system on chip ?

It wud be great if someone can proveide reference for this ?

-CA
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vivkr
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Re: Maximum on-chip variation in temperature for SOC
Reply #1 - Jun 12th, 2009, 12:05am
 
Hi,

I do not believe that there is any standard answer possible for that. Are you speaking of 2 different copies of the same circuit placed on a chip or 2 completely different kind of circuits?

The temperature depends on several factors like power consumption of a part, it's size, whether most of the power is burned in a few elements or overall, what sort of package you have, and also what other circuits are placed nearby and their power consumption etc. So, no general answer is possible.

Why do you want to know this by the way?

Regards,

Vivek
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cmos.analogvala
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Re: Maximum on-chip variation in temperature for SOC
Reply #2 - Jun 13th, 2009, 9:33am
 
I have a signaling shcme for global interconnects where driver and receiver are placed far apart. I want to see the performance of the scheme under worst case temperature mismatch. Let's say in an SOC Tx is at FFT unit and Rx is near memory block. What is the worst case temperature difference on the chip ?

-CA .
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ywguo
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Re: Maximum on-chip variation in temperature for SOC
Reply #3 - Jun 16th, 2009, 7:50pm
 
Hi CA,

I agree with Vivek. So it is difficult to have a standard answer now. But don't worry. Make your chip/system consume less power, use a package with good cooling system to reduce the temperature variation.


Yawei
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cmos.analogvala
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Re: Maximum on-chip variation in temperature for SOC
Reply #4 - Jun 17th, 2009, 9:54am
 
I just need a maximum possible number you might have seen. Say 10 degree, 20 degree or 50 degree C temperature variations you see ?

-CA
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