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banvetor

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Brazil

Parasitic capacitances in PIP capacitors
Jun 20^th, 2009, 3:43pm

Hi everybody...

I didn't know exactly where to post this question, but since I'm doing an analog design...

Well, I've been doing some layout of analog circuits in AMS 0.35 CMOS process. I use Tanner Tools as layout editor, and I'm seeing some strange behavior when extracting the layout with parasitic capacitances.

For instance, if I try to extract just the layout of a single PIP capacitor of approx. 200fF, I get parasitic substrate capacitances of about 70fF for the lower plate (poly1) and of about 210fF (!!!) for the upper plate (poly2).

From the AMS documents, I can see that the parasitic capacitances for poly 2 are a little bit SMALLER than for poly1, so this should not be the cause. Also, the poly2 plate is smaller than the poly1 plate, which should also contribute to lower parasitic capacitance in the upper plate.

I have tried extracting with and without a NTUB layer beneath the capacitor and nothing changed.

From the references that I've read, the poly2 parasitic capacitance should be smaller. Does anyone have any ideas of what may be causing this in my layout?

Thanks,
Leo.

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vivkr

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Re: Parasitic capacitances in PIP capacitors
Reply #1 - Jun 22^nd, 2009, 2:04am

Hi,

Unless you are doing something wrong (like accidentally placing some large nets on top of your cap), you should see negligible parasitic caps from the top plate (POLY2) to the substrate. The bottom-plate parasitic looks OK.

There may be some problem with the extraction tool setup. Contact your foundry interface, although this design kit should be relatively stable.

Regards,

Vivek

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banvetor

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Re: Parasitic capacitances in PIP capacitors
Reply #2 - Jun 22^nd, 2009, 6:52am

vivkr wrote on Jun 22^nd, 2009, 2:04am:

Hi,

Unless you are doing something wrong (like accidentally placing some large nets on top of your cap), you should see negligible parasitic caps from the top plate (POLY2) to the substrate. The bottom-plate parasitic looks OK.

There may be some problem with the extraction tool setup. Contact your foundry interface, although this design kit should be relatively stable.

Regards,

Vivek

Hi Vivek, thanks for your help... I indeed had a lot of contacts and metal on top of poly2 at first, but since discovering this problem with the parasitic capacitance I went to to even only 1 contact and the parasitics changed very little... Like from 210fF to 208fF.

It does seem that the extractor is summing up the actual capacitance value with the parasitic one for coming up with this total of 210fF of parasitic for a 200fF capacitor. But I have no idea how. I'm using Tanner v13 extractor, and the only configuration file is the extract definition file, which only has layers connections and devices definitions. Would you know any other places where this config could be on?

I know that Tanner v14 has a better parasitic extractor, HiPer PX, but I don't have the design-kit for this version yet...

Well, once again, thanks for your help.
Leo.

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Maks

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San Jose

Re: Parasitic capacitances in PIP capacitors
Reply #3 - Jul 1^st, 2009, 10:34pm

banvetor wrote on Jun 22^nd, 2009, 6:52am:

vivkr wrote on Jun 22^nd, 2009, 2:04am:

Hi,

Unless you are doing something wrong (like accidentally placing some large nets on top of your cap), you should see negligible parasitic caps from the top plate (POLY2) to the substrate. The bottom-plate parasitic looks OK.

There may be some problem with the extraction tool setup. Contact your foundry interface, although this design kit should be relatively stable.

Regards,

Vivek

Hi Vivek, thanks for your help... I indeed had a lot of contacts and metal on top of poly2 at first, but since discovering this problem with the parasitic capacitance I went to to even only 1 contact and the parasitics changed very little... Like from 210fF to 208fF.

It does seem that the extractor is summing up the actual capacitance value with the parasitic one for coming up with this total of 210fF of parasitic for a 200fF capacitor. But I have no idea how. I'm using Tanner v13 extractor, and the only configuration file is the extract definition file, which only has layers connections and devices definitions. Would you know any other places where this config could be on?

I know that Tanner v14 has a better parasitic extractor, HiPer PX, but I don't have the design-kit for this version yet...

Well, once again, thanks for your help.
Leo.

Leo -

it looks like your parasitic extractor extracts an intended, i.e. intrinsic, or device capacitance (of PIP capacitor), as parasitic. This will happen if you (rule deck) do not "block" the device capacitance extraction. "Blocking" means excluding intended capacitance from extraction. If this is true, you can either modify the rule deck to tell the extractor not to extract useful capacitance, or you can use the extracted capacitance value and exclude the device instance of the PIP capacitor from the netlist.

Max

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