Hi,ALL
I did not understand why the following verilog-A PFD of PLL can be described so simply.

integer state;
analog begin
@(cross(v(ref),+1,tttol) begin
    if(state>-1) state=state-1;
  end

@(cross(V(vco),+1,ttol) begin
   if(state < 1) state=state+1;
  end
I(out) <+ transition(Iout*state,0,tt)
end

Q 1 :  what is the initial number of state?
Q2 : in ref ,why stste>-1 then stste=state-1
      in vco ,why state<1  then state=state+1
sch