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Phase Mrgin (Read 1630 times)

raja.cedt Senior Fellow Offline Posts: 1516 Germany	Phase Mrgin Jun 27^th, 2009, 3:02am hi, � can any body please tell me how to find �degradation in PM because of delay in the loop? i saw in a pll thesis with td is the feedback delay wu is the unity gain loop bandwidth then phase margin degradation is 360wctd/2*pi..can any one please tell me �why they are using wu..i thought its fref(input frequency) Thanks, Rajasekhar.
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ywguo

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Shanghai, PRC

Re: Phase Mrgin
Reply #1 - Jul 1^st, 2009, 10:07pm

Rajasekhar,

What we use is the offset frequency relative to the carrier frequency in small signal analysis for PLL. A constant delay in the loop means different phase delay for frequency ω₁ and ω₂. It has nothing to do with fref (input frequency). The phase margin degradation is caused by the additional delay at the unity gain frequency ω_u.

360^o*ω_u*td/(2*pi).

Yawei

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