Designer’s Guide Community

icekalt

Community Member

Offline

Posts: 36
Aalen, Germany

confusion over an input signal of ADC
Jul 16^th, 2009, 1:53am

Halo,

When we say an input of 1.4Vpp, we can say that it is a sinusoidal signal from 0.7V to -0.7V. For folding ADC, the input is firstly connected to gate of differential pair. When the input voltage at the gate is from -0.7 to around +0.5 volt, the transistor is actually off. But we always want it to be on. I'm really confused over this. Can someone explain to me?

Back to top

IP Logged

yvkrishna Senior Member Offline Posts: 117	Re: confusion over an input signal of ADC Reply #1 - Jul 16^th, 2009, 10:18am hi icekalt, You are correct that the trans would go off, but the inp signal will be riding over a commonmode voltagel(DC voltage) to bias the transistors in saturation. And also most of the times the implementation is fully differential. Regards, Vamshi
Back to top	IP Logged

icekalt

Community Member

Offline

Posts: 36
Aalen, Germany

Re: confusion over an input signal of ADC
Reply #2 - Jul 16^th, 2009, 11:23am

yvkrishna wrote on Jul 16^th, 2009, 10:18am:

hi icekalt,

You are correct that the trans would go off, but the inp signal will be riding over a commonmode voltagel(DC voltage) to bias the transistors in saturation. And also most of the times the implementation is fully differential.

Regards,
Vamshi

Thx very much

so, is it ok to have -0.7 V to +0.7 V(1.4Vpp sinusoidal) input signal of diff. amp?? when i simulate the operating point, DC at the gate of transistor is 0 V

Back to top

IP Logged

yvkrishna Senior Member Offline Posts: 117	Re: confusion over an input signal of ADC Reply #3 - Jul 16^th, 2009, 11:43am what is the technology node and nominal supply voltage ? please post the snapshot of your circuit. Not clear what you mean by DC at gate is zero.. we have to apply additional DC voltage(for biasing trans in saturation) in series with signal voltage while simulation.
Back to top	« Last Edit: Jul 16^th, 2009, 1:06pm by yvkrishna » IP Logged

icekalt Community Member Offline Posts: 36 Aalen, Germany	Re: confusion over an input signal of ADC Reply #4 - Jul 16^th, 2009, 12:48pm yvkrishna wrote on Jul 16^th, 2009, 11:43am: what is the technology node and nominal supply voltage ? 0.35�m and 3.3 V supply voltage
Back to top	IP Logged

currant

Junior Member

Offline

Posts: 31

Re: confusion over an input signal of ADC
Reply #5 - Jul 16^th, 2009, 11:39pm

I think so:
1. If differential signal has Vpp=1.4V, then signal on one line has Vpp=0.7V. So we feed a signal �0.35 V to a gate of transistor.
2.Of course, we need apply to input of diff amp not only diff signal, but common mode voltage too. Vcm serves as DC offset of input stage (another variant, when dc offset is internaly formed, feed input signals through decoupling caps).

Back to top

IP Logged