aaron_do

Hi all,
suppose I want to design an LC tank and I have two options:
1. Use a large inductor with a low selfresonant frequency. At the resonant frequency of the tank, the L of the inductor is higher than its DC inductance. The parallel capacitor is either an MIM or the gate of a transistor.
2. Use a small inductor with a high selfresonant frequency. The inductance at the resonant frequency of the tank is the DC inductance of the inductor. Again, the parallel capacitor is either an MIM or the gate of a transistor.
Assume both designs have the same Q. So my question is, which option will result in less process variation? From my understanding, if we use option 2, the DC inductance will be quite accurate. However, i'm not sure if that matters since i'm connecting it to a parallel cap which will vary with the process. So it basically comes down to this: is the parasitic capacitance variation of an integrated inductor more or less than the capacitance variation of an MIM cap, or the cap at the gate of a transistor?
thanks, Aaron
