Dear Sirs,

                 I am using a CDK whose cells have schematic, symbol, layout and functional (verilog) views. Now for all the cells sch view has VSS and VDD inout pins (not globals)  but the symbol views don't have them. My problem is I am failing to declare VDD and VSS as global from ADE. When I use functional view of those cells, simulation(AMS)  goes smoothly, but when I use schematic  view of those cells simulation fails just because the cells' power grnd pins are not getting the desired voltage supposed to get passed  to them from TOP testbench. Please advise.