loose-electron wrote on Aug 9th, 2009, 6:28pm:there are a bunch of possibilities here - you can design a higher impedance system, you can swing lower voltages, you need to define your degrees of freedom, and also define the RLC network, the environment noise, etc, that you are trying to drive.
I totally agree. My biggest problem is that I don't understand the requirements of the LVDS buffer well enough to customize the interface. Second biggest problem is that I'm too lazy to look it up. ha ha. (Actually, I was just hoping to get a feel for what lies ahead by "poking my head over the cubicle" into this office and chit chatting about what I thought were easy questions.)
National has a great document out there on the subject, but it is 100+ pages!
Here is a schematic from maxim:
In the spirit of chit-chat, how is the common mode of the LVDS input determined? Could I drive the buffer with by switching it to 0 or 350mV? These are the things that aren't immediately obvious from reading the spec.