I am designing a 10G LC VCO w/ a tunable capacitor bank. What tests must one run to optimize the MOS switches that are in series with the capacitors? I can only think of the following:

1. On/Off ratio of capacitance at input of switch
2. Phase noise degradation due to Q of switch+cap combination.

Are the above steps a correct way of optimizing switch sizes? Any other way to optimize them?