i can't quite understand why gain boosting present doublets,
and what induce it in deed.
Though i have read the "A Fast-Settling CMOS Op Amp for SC Circuits with 90-dB DC Gain" , i can't understand the FIG 4.
Are there anyone who explain this to me.
thank you.

xwj623 wrote on Aug 5^th, 2009, 7:34pm:



Hi there,

The net output resistance (note that I stress on the word resistance) of a gain-boosted cascode is approximately

(1+Gboost)*Rout,cascode

At DC, Gboost is very high and it starts to roll-off as the frequency increases and you approach the unity-gain point of the boosting amplifier. Beyond that point, the net resistance flattens to Rout,cascode.

In other words, the impedance is first flat at a high level at very low frequencies, starts to roll off (a pole) and then flattens out again (a zero). This is all the auxiliary loop. In the main amplifier, you have a pole due to the gm of your opamp and the output load cap. So you have a pole-zero doublet.

Note however that the presence of the zero is the more critical part for settling since closed-loop poles are always attracted to open-loop zeros. So as long as you have open-loop zeros at a frequency lower than the closed-loop bandwidth, you will experience settling problems due to these.

By the way, the paper by Bult and Geelen explains the whole thing quite well. Go through it again, and also try Tom Lee's book on RFIC design. He covers this part there as well although not in the context of gain boosting.

Regards,

Vivek

raja.cedt wrote on Aug 6^th, 2009, 1:33am:


Hi Rajasekha,

I don't remember exactly but look in the sections dealing with lead/lag compensation. That should be in the chapter dealing with stability and compensation. But you don't need to see the book for that. Just think of a root locus. Here, the closed loop poles start where the open-loop poles were and end where the open-loop zeros were. By the way, this side discussion is now deviating from the original doublet discussion.

Regards,

Vivek

raja.cedt wrote on Aug 7^th, 2009, 2:21am:



Hi Rajashekhar,

Unfortunately, your figure is not quite complete and in any case, there is quite a good figure showing how the output impedance varies with frequency in the very first post of this thread, although the doublet itself is not visible from either as I have already mentioned in my first reply.

Regards,

Vivek

yes,vivkr.
i agree with you.

vivkr wrote on Aug 7^th, 2009, 6:49am:

hi vivkr and nobady,
                                 i agree with you..i just want to give a trail with some kind of wage explanation with out going into much circuit details..., in fig i forgot to add doublet at Z.

Thanks,
Rajasekhar.