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help me to evaluate my simulation result (Read 565 times)

icekalt

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Posts: 36
Aalen, Germany

help me to evaluate my simulation result
Aug 10^th, 2009, 3:44am

Hello everyone,

Please see my output waveform of my comparator in attachment. The comparator should make decision when the clock (Vclk) is low. Vp and Vn are the input of my comparator.Vout- is the output of my comparator. If you see the waveform, the output will be 3.3 although Vn is greater than Vp at certain time. For example, at 224.959ns, Vp is greater than Vn, but the comparator is in reset(no decison) in this time and the Vout- is appr. 1.7 V and it is fine. But when the clock is low, instead of comparing the present value of Vn and Vp, it compares the previous value of Vn and Vp that is at 224.959ns. Is this result ok or no? Is this what we called latency problem?

Thx in advanced

waveform_comparator_001.GIF

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mikro New Member Offline Posts: 3	Re: help me to evaluate my simulation result Reply #1 - Aug 18^th, 2009, 6:50am if i were u, i will recheck the logic vs schematic . if u wanna compare the inputs, which were present shortly before low-active, it is fine. if u wanna compare the inputs, which are present during low-active, it is not fine.
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Berti Community Fellow Offline Posts: 356	Re: help me to evaluate my simulation result Reply #2 - Aug 18^th, 2009, 10:42pm Latency problem? Never heard! To me it looks more like that your comparator has a large hysteresis. Reasons might be incomplete reset or bad settling of reference voltages. Cheers
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