hello,

I would like to run top level mixed signal (spectreVerilog) simulation where the power supply is ramped up from 0 to vdd. I need to reset all nodes inside the circuit to a known state because now I get unknown states for some internal nodes and spectre doesnt converge. Is there any switch (+sdf... or other way) I could use in the Simulation -> Options -> Digital tab to reset all nodes to 0V?

Thanks for your help.