Today I simulated the device noise of my swiched-capacitor sigma-delta modulator with the method using a ideal S/H to close the loop, as the designer's guide "Device Noise Simulation of sigma-delta modulators" said. The ideal S/H is implemented by Verilog-A as follows:
module sah_ideal(vin, vout, vclk);
input vin, vclk;
electrical vin, vout, vclk;
parameter real vtrans_clk = 1;
real vout_val;
analog begin
@(cross(V(clk) - vtrans_clk, 1.0))
vout_val = V(vin);
V(vout) <+ vout_val;
end
endmodule
The tran simulation may be OK, but when implementing a PSS simulation, the "vout_val" is refered as a hidden state and the PSS simulation is terminated. How to eliminate the hidden state so as to apply the S/H to the device noise simulation?
Thanks!
LUO