Dear all,

I'm evaluating a 1.8GHz VCO with a 4bit capacitor bank for coarse frequency tuning. Typically, for a given frequency channel, the PLL that includes this VCO can obtain lock for three neighbouring capacitor bank settings i, i+1 and i+2.

I notice quite a significant phase noise variation (~ +/2 dB) between the lowest (i) and highest band (i+2) for each frequency channel.

I know that the VCO phase noise varies in general versus this capacitor bank setting since it influences the Q of the tank, but normally the Q of the tank will not vary a lot for neighbouring bank settings (differing only in 1 LSB)....

Any insights on the mechanism causing this variation are welcome.

Regards

The bits are indeed binary weighted. I see the large variation between setttings differing in 1-2LSB. Difference in Kvco also came to my mind, I'm investigating this at the moment.

Regards