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kind of jitter for ADC (Read 5043 times)

Alexey New Member Offline Posts: 2	kind of jitter for ADC Aug 21^st, 2009, 7:03am Hello! I would like to know what kind of jitter is critical for ADC. I suppose that edge-to-edge, but I'm not sure �:(. May be cycle-to-cycle. I tried to find such information in PLLjitter.pdf but it is absent. Thanks in advance, Alexey.
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SSA@A

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Re: kind of jitter for ADC
Reply #1 - Aug 22^nd, 2009, 12:58am

I think this app note will help you. I like this because this note is simple and shows the relationship between SNR and Jitter.
National Semiconductor Application Note 1558
"Clocking High-Speed A/D Converters"
http://www.national.com/an/AN/AN-1558.pdf

When you need to evaluate the clock line, please refer to this app note.
Agilent Technologies Application Note 5989-5718EN
"Using Clock Jitter Analysis to Reduce BER in Serial Data Applications"
http://cp.literature.agilent.com/litweb/pdf/5989-5718EN.pdf

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Alexey New Member Offline Posts: 2	Re: kind of jitter for ADC Reply #2 - Aug 23^rd, 2009, 11:30pm Thank you, SSA@A! But it is not what I expected. Regards, Alexey.
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currant Junior Member Offline Posts: 31	Re: kind of jitter for ADC Reply #3 - Aug 26^th, 2009, 11:24am I think, in ADC we interest in value of edge-to-edge jitter, because the noise in signal appear over random difference beetwen edges of ideal and real clock.
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Mayank Community Fellow Offline Posts: 334	Re: kind of jitter for ADC Reply #4 - Jan 2^nd, 2010, 7:10am Hi, � � Refer to this post :--- �http://www.designers-guide.org/Forum/YaBB.pl?num=1260769814 It would surely help....Continue there if you have some doubts on it. -- Mayank.
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