Ken Kundert wrote on Sep 8th, 2009, 11:06am:
The problem is probably due to what you are connecting to the divider. Apparently you are trying to connect an electrical component to a phase port.
-Ken
Thanks for your reply. I still have some questions about the simulation of phase-domain model of PLL. The models are from your paper. The question are:
(1)As you know, when we do AC simulation, we should specify the stimulate source for ac, but as your model metioned, the port are phase type, which cannot be descibe by V** I**. how can I describe the phase source in netlist?
(2) In your mode, the top netlist mode is pll.va, which has no input source, just use the oscillator as input. when we simulate the testbench, the PLL just has one phase output port, has no input port, so the AC simulation will not take effect.
What's your suggestion? thank you very much
The attachment is the Hspice testbench of PLL phase domain model. The top netlist is as follows:
***phase domain simulation
.TEMP 25.0
.OPTION
*+ ARTIST=2
+ INGOLD=2
+ MEASOUT=1
+ PARHIER=LOCAL
*+ PSF=2
*.options probe
+ post=1
+ delmax=1e-10
.hdl "oscillator.va"
.hdl "divider.va"
.hdl "oscillator.va"
.hdl "phaseDetector.va"
.hdl "pll.va"
.hdl "vco.va"
.hdl "loopFilter.va"
xpll out pll
.AC DEC 10 1 1MEG
v1 clkin 0 AC 1 *PULSE 0 1.2 0 1e-9 1e-9 9e-9 20e-9
.end