Hi Yawei,

The following hints are valid for AMS Designer but I can't really tell how it ties with SpectreVerilog since I haven't used it for ages ...

First thing you may try to debug is to run a full transistor level simulation in SpectreVerilog, i.e using Spectre views everywhere including your digital libraries. You must have same results as a direct Spectre simulation. You need to contact Cadence otherwise. There are couple of instances where this may not be true in AMS Designer:
1. Veliog-A modules cmpiled differently
2. spectre version in AMS different from Direct Spectre.

In most cases (99 % may be), a direct spectre result matches a full spectre simulation in spectreVerilog/AMS.

So assuming the above was successful, i.e. you got same results, the next thing to look at is:

1. Whether the resolution of your connect modules is compatible with the Speed/Amplitude of signals you are dealing with.

2. Whether the digital libraries are well connected, especially look at the VDD/VSS as they are very likely to be inherited. Well, your graphs are very unlikely to suffer from this though.

3. In the log file, look at any odd warnings that occur in the spectreVerilog not in direct Spectre. A log file compare might be very helpful.

Hope this is helping,
Cheers,
Riad  :)