Quote:


That's true, but you won't be able to design highest-performance circuit with such a conservative approach.

Cheers

Hi MC,

Quote:

Assume the model is accurate, I think it depends on your design.

Quote:

I will choose the minimum sized MOS transistors for this case.


Best regards,
Yawei

Let me add my bit:

1. I would use a minimum-channel length: There is a clear metric for designing switches which says that Ron*Qinj = k/Lchannel^2, i.e. realizing a switch with a desired resistance level and a minimum possible charge-injection requires minimizing channel length. Look up your Razavi or work it out by hand.

2. In my opinion, it is far better to avoid loading your sensitive nodes with additional dummy switches in an attempt to "cancel" charge-injection. This works only at zero-order assuming the dummy switches really soak up the correct amount of charge, which is a very complex function of the risetimes, impedances seen in both directions by the switch etc. This works better for clock feedthrough and less for charge-injection.

3. Unless there is some very specific requirement for low "absolute error" due to charge-injection as in some high-precision sensor, or your technology is really lousy (in which case dummy switches are probably also lousy), I would simply worry about avoiding "signal-dependent charge-injection" and forget about fixed charge-injection. Use bottom-plate sampling (a delayed clock phase to open the signal-dependent floating switches), and a differential architecture for your circuit. The above scheme is like taking an aspirin for a headache. There may be several causes and/or effects but in most cases, your headache will be cured (not my own).

4. If on the other hand, you really want to know more about charge injection, then there are papers by Eric Vittoz and his student George Wegmann (look up old JSSC). There are also several other circuit techniques which supposedly reduce charge injection, but most provide only a limited benefit for large costs. One such example that I can recall is where the authors used a switched opamp instead a switch. The reasoning was that the opamps output stage which is acting as a switch has transistors in saturation (channel pinched off near the drain), and so when they are turned OFF, then the charge flows towards the source end and you have less charge injection. As you can guess, there are very many conditions that need to be met for this scheme to really work well, plus you have an opamp for each switch.

5. Boosting the gate (or a fixed gate-source overdrive) may provide a more signal-independent charge injection level but would barely suffice on its own (on top of being a more complex scheme). I would stick with bottom plate sampling as I mentioned above.

Regards,

Vivek

loose-electron wrote on Oct 6^th, 2009, 11:22pm:


agree fairly with you Jerry, but a couple of points:

1. While transistor models may not be very accurate, they are getting better all the time, and a mature process may not have such bad models. In any case, the local impedances at source/drain may be more important than unmodelled NQS effects in most cases => better sim accuracy.

2. I found dummies to be of limited use while working on 20bit, 100 kHz systems. They are huge (dummy switches as big as main switch), and although speed is low, so is the power budget (and managers with knowlege of the inverter power consumption CV^2f think that systems at a few kHz should anyway need zero power, since their Excel sheet shows frequency in GHz to 2 digits after decimal . My point is that you can probably do better than using dummies, unless you are making uncalibrated absolute-accurate incremental ADCs.

3. You mention adding 4 transistors, 2 as the pass gate (1 P + 1 N I assume), but surely you also need a P and an N on either side to do the charge cancellation with the dummy, and would have 6 transistors that way.

Regards,

Vivek

The use of 2 transistors in parallel is a modeling trick, all 4 transistors are exact same geometry, and that way the charge cancellation is (in theory, and this is a time to NOT trust simulation results!) balanced.

The switch I was describing (with 4 transistors) is a PMOS only or NMOS only structure. If you want wide range (NMOS with PMOS pass gate) then it gets even messier with a total of 8 transistors in the switch.

Generally I would not go there.

As for models getting better? Sorry, but I strongly disagree and agree at the same time. Almost always models lag silicon by a generation or two (or three or...) and the "chicken and egg" analogy (which comes first) applies.

Also, almost all models the parameters are not properly set for specific items that are extremely difficult to measure and this includes the charge holding capacitors that are non-linear(junction depletion capacitance of drains and sources come to mind, as well as channel inversion charges) as a rule these are not set properly.

As well a cautionary comment - Just because a foundry claims they have the "latest and greatest BSIMX.X" models does not really mean much. I have done foundry model audits and when you get inside the details of the model you find that 80% of the parameters are not set properly (or at the default value) and what you really have is a much older and simpler model due to the fact that the  they never used most of the parameters in the transistor model.

Jerry

Mismatch with min L switchs is bigger although charge injected might be not as bigger as mismatched area in ratio sense.  I think one should do careful simulation to find an optimized L for given frequency.  Min L might not be optimized value.  Min L causes bigger leakage and it will cause bigger error.  For higher frequency sampling clock it may force you to use Min L.  If frequency not high, it is better to use bigger L than min L, mismatch is smaller and PVT effect is smaller.

Here you go -

Important note - the Top transistor is 2 devices in parallel - and there are a total of 4 transistors all the same size.

The gate control for the bottom pair of transistors is the complement of the gate control that drives the top two transistors.

Not a problem - this has been around for a while - - since at least 1980 - look at the schematic it was drawn when 0.6 micron transistors were state of the art.