loose-electron wrote on Oct 6th, 2009, 11:22pm:As with many engineering decisions, this is one where you are going to have multiple solutions, and several solutions that all work well. Charge compensated switches are generally not used at high frequencies (excessive capacative loading yes..) but is still commonly used for lower frequency sampling systems in order to keep the holding capacitor sizes smaller.
However simulations of these things are often misleading due to inaccurate transistor models, the usual methodology is 4 transistors, two in parallel as the switch, and one on each of the drain/source as a dummy driving capacitance, with complementary gate signals. (All 4 transistors have the same geometry) The methodology has been in used for quite a while.
agree fairly with you Jerry, but a couple of points:
1. While transistor models may not be very accurate, they are getting better all the time, and a mature process may not have such bad models. In any case, the local impedances at source/drain may be more important than unmodelled NQS effects in most cases => better sim accuracy.
2. I found dummies to be of limited use while working on 20bit, 100 kHz systems. They are huge (dummy switches as big as main switch), and although speed is low, so is the power budget (and managers with knowlege of the inverter power consumption CV^2f think that systems at a few kHz should anyway need zero power, since their Excel sheet shows frequency in GHz to 2 digits after decimal
. My point is that you can probably do better than using dummies, unless you are making uncalibrated absolute-accurate incremental ADCs.
3. You mention adding 4 transistors, 2 as the pass gate (1 P + 1 N I assume), but surely you also need a P and an N on either side to do the charge cancellation with the dummy, and would have 6 transistors that way.
Regards,
Vivek