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Mayank

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Non-Linearity Effects of Opamp on Error Amplifier
Sep 16^th, 2009, 9:46pm

Hi,
I am designing an error amplifier, topology being rail-to-rail i/p Single-Ended Folded Cascode. In 65nm process, because of low gm/gds values + max. vov requirements set by desired o/p swing, i need to bias the pMos-load transistors in sub-threshold region. But vds available to me is just 150mV which is barely 6 times kT/q, making id characterstics of these load MOSFETs highly dependent on vds in sub-Vt region.
I think this non-linearity should be tolerable if the gain of opamp is sufficient to keep my error voltage within specs ?? I am confused as to what other effects will it have ?

Regards,
mayank.

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subgold

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Re: Non-Linearity Effects of �Opamp on Error Amplifier
Reply #1 - Sep 17^th, 2009, 1:39am

Mayank wrote on Sep 16^th, 2009, 9:46pm:

Hi,
I am designing an error amplifier, topology being rail-to-rail i/p Single-Ended Folded Cascode. In 65nm process, because of low gm/gds values + max. vov requirements set by desired �o/p swing, i need to bias the pMos-load transistors in sub-threshold region. But vds available to me is just 150mV which is barely 6 times kT/q, making id characterstics of these load MOSFETs highly dependent on vds in sub-Vt region.
� I think this non-linearity should be tolerable if the gain of opamp is sufficient to keep my error voltage within specs ?? �I am confused as to what other effects will it have ?

Regards,
mayank.

what is your supply voltage? 150mV of vds is not small at all, in fact, i would say it is quite large for typical supply voltage in 65nm. plus, this vds is relatively constant. i dont think that is the main source of the nonlinearity, because the linearity is depending on the bias current variation versus the input. what i am curious about is how you gonna realize the rail-to-rail input. if you use multiple input pairs, then you need to regulate the total bias current of your input stage, because that is the main source of the nonlinearity.

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Mayank

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Re: Non-Linearity Effects of Opamp on Error Amplifier
Reply #2 - Sep 17^th, 2009, 2:52am

Hi subgold,
my supply is 1.2 and i am building this opamp for vds matching in an active cascode kind of v2i convertor for a vco.
I simulated normal pfet for id vs vds characterstics for diff. vgs in sub-vt region and they show linear region after 250mV which i cant afford. Shall i bias these load transistors in sub-vt ??
As for i/p MOSFETs' gm , i am using a constant gm ckt for biasing.
My main question is, what is the main effect of NON-LINEAR GAIN of this error amplifier on current injeccted into VCO ?

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raja.cedt

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Re: Non-Linearity Effects of Opamp on Error Amplifier
Reply #3 - Sep 17^th, 2009, 9:57pm

hi Mayank,
why you want voltage to current converter for an VCO (i guess it is ICO)..i feel rail to rail is not required for gain boosting amp because your control node voltage wont move from vss to vdd and why you want to use sub threshold region because sub threshold is highly non linear region when compared to sat or triode mode. And as subgold mentioned for now a days technologies vds is 150mv is very good.

If possible please post your circuit

Thanks,
Rajasekhar.

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