Mayank wrote on Sep 16th, 2009, 9:46pm:Hi,
I am designing an error amplifier, topology being rail-to-rail i/p Single-Ended Folded Cascode. In 65nm process, because of low gm/gds values + max. vov requirements set by desired o/p swing, i need to bias the pMos-load transistors in sub-threshold region. But vds available to me is just 150mV which is barely 6 times kT/q, making id characterstics of these load MOSFETs highly dependent on vds in sub-Vt region.
I think this non-linearity should be tolerable if the gain of opamp is sufficient to keep my error voltage within specs ?? I am confused as to what other effects will it have ?
Regards,
mayank.
what is your supply voltage? 150mV of vds is not small at all, in fact, i would say it is quite large for typical supply voltage in 65nm. plus, this vds is relatively constant. i dont think that is the main source of the nonlinearity, because the linearity is depending on the bias current variation versus the input. what i am curious about is how you gonna realize the rail-to-rail input. if you use multiple input pairs, then you need to regulate the total bias current of your input stage, because that is the main source of the nonlinearity.