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VINAY RAO

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Abt CADENCE VERILOG-XL PROBLEM in AMS DESIGN
Sep 18^th, 2009, 2:29am

HI,
I am facing many problems while openening VERILOG-XL in CADENCE.If i am going to V-XL through schematic (as tool-simulation-verilog-xl-setup enironment-run directory(ex:mos.run1)) after setup env's ok ,its showing the error as "INVALID VERILOG EXECUTABLE VERILOG,Please check existance and for permissions and try again,relative path names are relative run directory"...If i clsose the simulation option warning then verilog-xl window is opening..after setng up the environment and start interactive(simulation) in between error is coming..That error is "user-settable variable:verilogsimbinary is invalid.,Relative path names are relative to run directory"..
simulation is gtng aborted.If i am opnng directly thru the CIW window its shwng the same prob..
Hw cn i solve this prob???.
Pl reply soon,,pl if u dnt know ,pl ask ur administrator and help me..i am runnng out of time in my project...Its my humble request..
Thank you..

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Riad KACED

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Swindon, UK

Re: Abt CADENCE VERILOG-XL PROBLEM in AMS DESIGN
Reply #1 - Sep 21^st, 2009, 1:05pm

Hi Vinay,

The verilog executable is either not installed in your environment or not acquired. In fact, the verilog is not part of your IC stream (assuming IC5). Ask your administrator for LDV/IUS. You need to install one of these streams or update your PATH variable to acquire them if already installed.

Cheers,
Riad.

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Riad KACED
PDK, EDA Support Engineer.

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VINAY RAO Community Member Offline Posts: 74	Re: Abt CADENCE VERILOG-XL PROBLEM in AMS DESIGN Reply #2 - Sep 30^th, 2009, 4:44am Thank you very much..we got IUS,ya i hv to instal that..We got IC5141,SOC,ASSURA,and IUS..what more tools are required for full mixed design flow??.
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Riad KACED Community Member Offline Posts: 93 Swindon, UK	Re: Abt CADENCE VERILOG-XL PROBLEM in AMS DESIGN Reply #3 - Oct 1^st, 2009, 8:53am Hi, IC5141 and IUS are the only stream required to run AMS Designer in the Virtuoso use model. I have already answered this question in another thread of yours ... Cheers, Riad
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VINAY RAO

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Posts: 74

Re: Abt CADENCE VERILOG-XL PROBLEM in AMS DESIGN
Reply #4 - Oct 1^st, 2009, 10:08am

hi,
Thanks a lot Riad,,,i posted 1 more question regardng running of IC 5141,,can u check it out pll??..And 1 more thing u told me that ,its better to opt for AMS Designer in ADE mode (not HED) with OSS based netliting.How can i select this mode?? (while installing or while making the designs)..?
Thank you,
Regards,
VINAY RAO

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Riad KACED

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Posts: 93
Swindon, UK

Re: Abt CADENCE VERILOG-XL PROBLEM in AMS DESIGN
Reply #5 - Oct 2^nd, 2009, 12:31am

HI,

It's at design level.
You better look at the docs I suppose.
I would advise:

Virtuoso� AMS Designer Simulator User Guide, available from your IUS82 steam at $IUSHOME/doc/ amssimug /amssimug.pdf
Virtuoso AMS Environment User Guide, available from your IC stream at $CDSHOME/doc/ amsenvug /amsenvug.pdf
AMS Designer in ADE FAQ, available from your IC stream at $CDSHOME/doc/ AMSinADEFAQ/AMSinADEFAQ.pdf

Well, you better use the cdnshelp search utility.

Cheers,
Riad.

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Riad KACED
PDK, EDA Support Engineer.

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