veerendra wrote on Sep 20th, 2009, 11:46pm:Is it possible to design 10bit 4MSPS cyclic ADC with 0.5mW Power onsumption in 90nm with 1v supply?.
That is a very strange question. Do you want to design a 10b ADC or do you want only a cyclic ADC? It could also be SAR for instance.
Anyway, as to whether something is possible or not depends entirely on the ingenuity of the designer, but taking into account the figure of merit requirements, in this case
FOM = Power/(2^ENOB*Fs), where I liberally assume ENOB = N = 10 bits, we come to 122 fJ/step. That is aggressive but considering that you are aiming for a 10 b ADC which is on the lower end of resolution and your ENOB probably can be as bad as 9.5 or even 9 bits, I would say it is doable.
By the way, there are a few 10 b ADCs that would meet those FOM requirements (look through the high-speed ADC sections at ISSCC), although they aim for much higher speeds. My advice would be to use a SAR ADC, with some redundancy in it. Check out the paper by Kuttner at ISSCC (I think it was 2001 or 2002).
Regards,
Vivek