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glitches in the output of DAC (Read 6245 times)
icekalt
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Aalen, Germany
glitches in the output of DAC
Sep 23rd, 2009, 7:25am
 
Hi,

Firstly i connected my 8-bit Folding ADC with an ideal DAC so that i can do FFT translation. What is annoying me so much is the glitch at the output of ideal DAC when i simulate the circuit with the speed of clock of 50MHz.At 25 MHz clock, the glitches do not appear at all.  You can see the glitch at every every period of the wave when the Vout(DAC output) is 0V. What causes this?
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DAC_Output.jpg
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ywguo
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Re: glitches in the output of DAC
Reply #1 - Oct 6th, 2009, 8:31pm
 
Hi icekalt,

Does the DAC operate at clock edge or any transition of input data? The DAC needs to be triggered by a clock, otherwise any competition of the input data results the glitches.

Yawei
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icekalt
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Re: glitches in the output of DAC
Reply #2 - Oct 7th, 2009, 5:41am
 
ywguo wrote on Oct 6th, 2009, 8:31pm:
Hi icekalt,

Does the DAC operate at clock edge or any transition of input data? The DAC needs to be triggered by a clock, otherwise any competition of the input data results the glitches.

Yawei


Hi Yawei,

The DAC operates at clock edge. It is an ideal DAC. I think the problem comes from the digital/encoder part of my circuit(see attachment). When the sampling rate is over than 30 MHz, then the glitches appear.  It works fine. I heard something about clocking the digital part but i don't know how
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exor_encoder.jpg
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ywguo
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Re: glitches in the output of DAC
Reply #3 - Oct 9th, 2009, 7:25pm
 
Hi icekalt,

Do you clock the encoder output to registers/DFFs? If NOT, the output must be unstable at the begining of each conversion cycle because the combinational logic has race hazard. http://en.wikipedia.org/wiki/Race_hazard
In your testbench, the unstable encoder output is clocked to the ideal DAC after the sampling rate is increased to 30MS/s, i.e., the cycle is decreased to 1/30M.
1. Delay the phase of clock for DAC, waiting for the stable encoder output.
2. Put registers/DFFs at the encoder output.


Yawei
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