Via resistance in all processes changes a huge amount over foundry wafer lots from the exact same foundry and process.. If it is nominally 1 ohm, the expectation of it to change from 0.5 ohms to 2-5 ohms should be designed for.

Safe premise: Always use enough via connections that the resistance of the vias is not enough to affect the design.

Bottom Line: lots of vias in parallel

Low is a matter of perspective. To someone putting large currents in an IC, the resistance of the layer change has been very problematic.

Via interconnects have been an issue with high current power transistors, RF power amps,  H bridge motor drivers and other areas.