Hi Balu,

This indicates to me that your pipeline stage is not accurate enough. Note that you will anyway never get the exact residue. The question is simply whether the resulting error is small enough to meet your spec.

Here are a few possible things I can imagine going wrong in your design:

1. Insufficient transient gain (i.e. virtual ground at opamp input not sufficiently accurate at the end of the settling phase). Note that it is largely pointless to look merely at AC simulations of DC gain and bandwidth. You need to also look at settling of the entire MDAC under correct loading and operating conditions.

2. Offset due to charge-injection. If you are using a good switching scheme and have only fixed signal-independent charge-injection, then you probably don't care. Otherwise, you need to fix those switches.

3. Capacitor mismatch. This is probably not there in your simulations anyway.

4. Comparator offset. There will likely be some systematic offset depending on your design which will move the transition points of your residue transfer curve. You may even have some hysteresis.

The list can be extended arbitrarily but you can concentrate on these major factors, particularly 1.

Regards,

Vivek