sand_dolphin2,
According to sec. 4.5.15 in  the Verilog-AMS LRM (version 2.3.1, http://www.designers-guide.org/VerilogAMS/vams231.pdf) analog operators (such as laplace_xx) are not allowed inside if/case etc. statements (unless using constant expressions). Poles and zeros may not change either (cf. sec. 4.5.14).
One possiblity is to use 3 filtered internal signals: Code:

analog
begin
   V(out750k)	<+ laplace_nd( V(in), { num0 }, {den0, den1_750k} );
   V(out1M5)	<+ laplace_nd( V(in), { num0 }, {den0, den1_1_5M} );
   V(out3M)	<+ laplace_nd( V(in), { num0 }, {den0, den1_3_0M} );
   if(FREQSEL == 2'b00)
	V(out) <+ V(out750k);
   else if(FREQSEL == 2'b01)
	V(out) <+ V(out1M5);
   else //if(FREQSEL == 2'b10 or 11 or x)
	V(out) <+ V(out3M);
end 

This requires 3 internal signal nodes, so it may not be a very efficient solution.  And when switching, the signal will usually jump.
Of course, there are other options to solve this as well. Which solution is best depends on your requirements.
BOE

Hi

laplace (like all analog operators), if used in conditional/loop blocks,  can only be used inside ones governed by genvars.

The arguments are "Constant expressions". This does not mean that variables are not allowed (4.5.14, see the note after table 4-20) or that there is a restriction where variables are used. It just means that the simulator must take the fist values.

So you should be able to write something like

  real den [0:1];

analog begin
    den[0] = den0;
   
    if(FREQSEL == 2'b00)
      begin
       den[1] = den1_750k;
      end
    else if(FREQSEL == 2'b01)
      begin
       den[1] = den1_1_5M;
      end
    else //if(FREQSEL == 2'b10 or 11 or x)
      begin
       den[1] = den1_3_0M;
      end

    V(out) <+ laplace_nd(V(in), {num0}, den);

Paul

All,

I responded to Sand Dolphin privately last week, seeking a short contract from his company, but with no luck ;-(

I did share the following hint with him and now I'm sharing it with others following this thread:

Sand Dolphin,
The problem you describe is straightforward to solve.  One solution is based upon differential equations in the form of state equations.  You must also use certain analog modeling principles which may be found in Ken Kundert's book "Designer's Guide to Verilog-AMS".

Cheers,
Robert Peruzzi
www.RPeruzzi.com

sand_dolphin2,
Paul Floyd's code limits you to one bandwidth per simulation run. If you need to change FREQSEL/the bandwidth during a simulation run, you can
1. use my "lazy" code from reply #1, which I created it within one or two minutes from yours (however it requires additional internal nodes as already mentioned), or
2. write your own filter model as Peruzzi suggested (requires less internal nodes so it should simulate better/faster, and also allows modeling the switching transition).

BOE