I have a question concerning the PSRR of the bandgap.

I have a sub-1V current summing bandgap topology. I use a cascode transistor in the output branch to improve the PSRR.

then I add a regulation loop around the cascode transistor (gain-boosting) to further improve the PSRR. Then the problem arises. The PSRR improvement can only go up to a certain level, and can go no more higher, even if I increase the gain of gain-boosting amplifier, which would theoretically increase the output impedance of the cascode branch.

Also, the loop composed by the opamp has a rather high gain and PSRR, which doesn't seem to be the limiting factor here, does it? i am not so sure how this loop will eventually impact the PSRR.

Can anybody give me a clue on what is limiting the PSRR in this case?
Thanks a lot.

Hi subgold,
                I dont know whether u are talking about schematic level design OR Post-Layout Simulation, But in any case, Take care while PNR to keep the capacitance between the opamp o/p node and the vdd/vss rails to be negligible(this cap will directly introduce coupling, hence degrading supply rejection). Especially in BG ckts, Layouts are v critical...

thanx,
Mayank.