Hi.
I have the following code:

integer Rand;
Rand = $random;
$write("Rand = ");
$write(Rand);

The random function is the correct syntax, as checked by the compiler and me vs the reference manual. Rand and random are both 32 bit integers. My problem is that as soon as the VerilogA code gets to this line it gives a Bus Error, with the message to send Cadence the netlist (i.e. totally unhelpful).

I would rather use the normal distribution function as such:

integer Rand;
Rand = $dist_normal(seed, mean, standard deviation);

But this code gives me a value that is always the same and always saturated near to the mean point. I would for example like a random number uniformly distributed between -50 and +50, with a mean of zero and a standard deviation of 20.

Removing just the Rand = line of code, the module correctly simulates. Its not a syntax issue as the code compiles correctly. Why is this happening. It shouldn't be a memory error as I'm running on a Sun Blade 1500 with 2Gb RAM.

Thanks.
Ed